Fully Buffered DIMM (or FB-DIMM) Dynamic Random Access Memory (DRAM) memory devices provide a memory solution that can be used to increase reliability, speed and density of memory systems. Traditionally, data lines from a memory controller are connected to data lines in every DRAM module. As memory width, as well as access speed, increases, the signal degrades at the interface of the interconnect and the device. This limits the speed and/or the memory density. FB-DIMM devicers take a different approach to solve this problem.
The FB-DIMM architecture includes an Advanced Memory Buffer (AMB) between the memory controller and the memory module. Unlike the parallel interconnect architecture of traditional DRAMs, a FB-DIMM has a serial interface between the memory controller and the AMB that enables an increase to the width of the memory without increasing the pin count of the memory controller beyond a feasible level. With this architecture, the memory controller does not write to the memory module directly, rather it is done via the AMB.
FB-DIMM devices typically allow the memory controller to pack up to three memory commands in one frame. The duration of one FB-DIMM frame is one DRAM command. Thus in FB-DIMM based memory controllers, the memory controller theoretically has an opportunity to transmit three DRAM commands in one cycle.
Practically, however, two Read Column Address Strobes (CAS) commands cannot be transmitted back to back in a single FB-DIMM channel because of contention in the memory to memory controller (e.g., or northbound (NB)) FB-DIMM lanes. For instance, the memory controller typically has to provide one no operation (NOP) frame between two read CAS commands for a read having a burst length of four.
The NOP frame is inserted to slow down the commands so that data doesn't overlap for different read commands. Thus, the insertion of the NOP frame restricts a host from sending three read CAS commands in a single FB-DIMM frame. Due to this restriction, most of the designs include a single command mode for keeping the memory controller scheduler simple.
Designs that incorporate a three command mode, face complexity issues in resolving conflicts between the commands before scheduling. A problem exists in one command scenarios in which every write command introduces a minimum two idle frames in NB lanes.